Eriemon

This skill is for Chinese-language Verilog or RTL design, existing-RTL analysis, verify-repair planning, controlled refinement, semantic comparison, debugging, and static lint. It also covers self-checking testbench scaffolds and ASIC-quality review for Verilog-target designs, including synthesizable Verilog-2001 RTL and Vivado/xsim validation.

Use for HLS development, design, modification, and debugging, including high-level synthesis with Vitis HLS, AMD/Xilinx HLS, C/C++ kernels, pragmas, DATAFLOW, array partitioning, and analyzing HLS reports or RTL issues.

This skill is used for managing AGENTS.md and AI coding-agent rule files, including creation, updates, verification, and review. It's also applicable when AGENTS.md is missing, has mismatched version metadata, or when the user refers to AGENTS.md, agent rules, or the current workspace.

Use when Codex needs to manage GitHub repositories via gh CLI or GitHub APIs. This includes tasks like handling issues, pull requests, CI, releases, branch protection, security audits, and repository governance.