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vf-rtl

Use this skill to start or resume the VeriFlow RTL hardware design pipeline (architect to synth). Trigger this when the user asks to "run the RTL flow", "design hardware", or "start the pipeline". Pass the project directory path as the argument. Optional: append `--benchmark` to auto-generate a benchmark report after the pipeline completes.

19stars
Updated 18 days ago

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How to add

/plugin marketplace add bjwanneng/veriflow-cc

The exact command may vary by repository. Check the README on GitHub.

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Drop this on your repo README

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