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Circuit Optimizer
Purpose
Provides expert guidance on quantum circuit optimization techniques for reducing gate count, minimizing depth, and adapting circuits to hardware constraints.
Capabilities
Circuit depth reduction algorithms
Gate cancellation and merging
Peephole optimization
Template matching optimization
Commutation analysis
Hardware topology-aware routing
Two-qubit gate minimization
Compilation pass orchestration
Usage Guidelines
Analysis: Profile circuit for optimization opportunities (gate counts, depth, connectivity)
Gate Reduction: Apply cancellation and merging rules for equivalent gates
Depth Optimization: Parallelize independent operations where topology allows
Hardware Mapping: Route circuits to respect hardware connectivity constraints
Verification: Validate circuit equivalence after optimization
